The present invention relates generally to digital memory devices, and in particular to output paths for memory devices.
Memory devices such as synchronous dynamic random access memory (SDRAM) devices are widely used to store data in computers and electronic products. An SDRAM device typically has a large number of memory cells. The memory cells are usually arranged in rows and columns.
Data are read from the memory cells by a read operation. In some SDRAM devices, a read operation transfers one bit of data from one memory cell to an output data pad within one clock cycle. In a double data rate (DDR) SDRAM, two bits of data from two memory cells are transferred to an output data pad in one clock cycle during a read operation.
A DDR SDRAM typically accesses two data bits at a time from the memory cells, and transfers them via a data path; so that one bit can be read to the data pad on a rising clock edge, and the other on the next falling clock edge. Previous data paths, however, take longer than necessary to deliver the data bits to the data pad, and queue up the data bits unnecessarily.
There is a need for a DDR SDRAM having improved data paths to transfer a first bit of data to a data pad via shortest path during a read operation.
The present invention provides a memory device having an improved data path to transfer a first bit of data to data pads via a shortest path.
One aspect provides a memory device including a main memory, a plurality of data pads, and a plurality of data paths connected between the main memory and the data pads. Each of the data path transfers a first and second bits of data from the main memory to a data pad in one clock cycle during a read operation. The first bit of data is transferred to the data pad in a shorter path than the path of the second bit of data.
Another aspect provides a method of transferring data in a memory device. The method includes receiving a first data bit at a first data sense amplifier and receiving a second data bit at a second data sense amplifier. The first data bit is transferred through a first output path to a data pad, and the second data bit is transferred through a second output path to the data pad. The first data bit takes less time than the second data bit, and both the first and second data bits are completed in one clock cycle.